Buses carrying digital data on multiple parallel data lines may be used in numerous applications, e.g., for connecting integrated circuits to each other or for connecting printed wiring boards. In such an application, a transmitter for sending data on a bus may have a plurality of input/output (I/O) circuits, one per data line, each switching the voltage on the data line between two values. For example, if a data line is implemented as a single conductor and a ground, e.g., as a printed wiring board (PWB) trace over a ground plane, an I/O circuit may drive the conductor with a positive voltage to signal a logical 1 (i.e., high), or with a voltage near ground to signal a logical 0 (i.e., low). In other examples, a data line may include more than one conductor in addition to, or without, a ground conductor. For example, differential signaling may be used with two conductive traces, a first trace and a second trace, over a ground plane on a PWB, and the I/O circuit may drive the first trace and the second trace in a complementary manner, so that, e.g., at any point in time, the current carried by the second trace is substantially equal in magnitude as the current carried by the first trace, and in the opposite direction.
The I/O circuit may draw relatively high current from the power supply when it is transitioning between states, e.g., from a logical 1 to a logical 0, or vice versa. This current draw may cause a fluctuation in the higher power supply voltage (VDD) or the lower ground voltage (VSS) or both. The fluctuation in VDD may differ in magnitude from the fluctuation in VSS. For example, if a PWB trace is used to provide VDD and a ground plane is used to provide VSS, in which case the source impedance of VDD may be greater than that of VSS, and the change in voltage resulting from an increased current draw may primarily affect VDD.
In a synchronous system, on a bus with multiple parallel lines, several I/O circuits may, on occasion, switch simultaneously, exacerbating the fluctuations in VDD and/or VSS. This effect is referred to as simultaneous switching output (SSO) noise. The magnitude of SSO noise may be reduced by installing power supply decoupling capacitances, each of which may be composed of a single capacitor or of several capacitors connected in parallel, or by increasing the number or size of the capacitors of which the power supply decoupling capacitances are composed. In some implementations, however, the space area available on the silicon, or in the package, or on the PWB for such capacitors may be limited, constraining the extent to which this mitigation technique may be used.
SSO noise may limit an I/O interface's electrical performance, e.g., it may limit the speed at which the I/O interface may be operated. Thus, there is a need for a system and method for reducing SSO noise.